This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-316824, filed on Oct. 15, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to an insulated gate semiconductor device.
2. Related Background Art
FIG. 10A shows a partial cross-sectional view of a non-punch-through-type and vertical-type IGBT (insulated gate bipolar transistor) taken as a prior art of insulated gate semiconductor device. This IGBT 10 includes an n-type base layer 13, and a p-type base layer 14 formed on the base layer 13. The p-type base layer 14 includes an ne-type source layer (cathode) 15 formed in a selective top surface region thereof. A p+-type drain layer (anode) 11 underlies the bottom surface of the base layer 13 opposite from the top surface thereof. A gate electrode 16 is formed in the base layer 13 so that the gate electrode 16 makes a channel in the p-type base layer 14 for electrical conduction between the source layer 15 and the base layer 13. The gate electrode 16 is insulated from the base layer 13, source layer 15 and p-type base layer 14 by an insulating layer 17.
In IGBT 10, the base layer 13 must be relatively thick, or relatively low in specific resistance to prevent that the depletion layer from the p-type base layer 14 reaches the anode when it is turned OFF. As a result, the tail current during turnoff period undesirably increases. Therefore, to attain a high-speed turnoff property, injection efficiency of hole current from the anode is reduced by lifetime control. Typically, lifetime control is carried out by annealing the wafer by irradiating an electron beam after completion of the wafer process.
This process of lifetime control, however, invites a decrease of the carrier concentration in the high-resistance nxe2x88x92-type base layer 13, and thereby undesirably increases the ON voltage. If nothing is done for shortening the lifetime, the ON voltage will be maintained low, but the turnoff time will be elongated. That is, the ON voltage and the turnoff time are related to trade off relation.
FIG. 10B shows a partial cross-sectional view of a punch-through type and vertical type IGBT taken as another prior art. This IGBT 20 is different from IGBT 10 in including an n+-type buffer layer 23 interposed between the nxe2x88x92-type base layer 13 and the p+-type drain layer 11.
Because of the existence of the n+-type buffer layer 23, the depletion layer from the p-type base layer 14 does not reach the anode even when the nxe2x88x92-type base layer 13 is relatively thin or has a relatively high resistance. Therefore, IGBT 20 can maintain a resistivity to voltage even if the nxe2x88x92-type base layer 13 is thinner or lower in resistance than IGBT 10.
Additionally, injection efficiency of hole current in IGBT 20 is controlled by thickness or concentration of the p+-type drain layer 11. Therefore, IGBT 20 has been improved toward higher switching speed without lifetime control.
Another type of IGBT operative at a switching speed as high as approximately 150 kHz has become known recently. However, any of high-switching-speed IGBTs including the above-mentioned IGBT 20 suffer a tail current that increase under high temperatures. Tail current becomes switching loss, and the switching loss disturbs high-speed switching of IGBT.
FIG. 11 shows changes of current and voltage characteristics of L (inductance) loaded IGBT 20 in response to the time during turnoff period of IGBT 20. When the gate voltage VG decreases and the electron current flowing to the channel decreases, opposite-electromotive force is generated across opposite ends of the L load. The opposite-electromotive force is applied between the anode and the cathode, and the drain voltage VD rises (seethe portion from time t1 to time t2).
With the drain voltage VD, a depletion layer (not shown) is generated from the junction between the high-resistance nxe2x88x92-type base layer 13 and the p-type base layer 14. The depletion layer permits electrons heretofore accumulated in the high-resistance nxe2x88x92-type base layer to be supplied to the electron current from the channel. As a result, IGBT 20 behaves to have a constant drain current ID to flow. Therefore, a substantially constant hole current flows from the p+-type drain layer 11. That is, in the period from time t1 to time t2, the drain current ID is maintained approximately constant.
Electrons having accumulated in the nxe2x88x92-type base layer are exhausted eventually. Accordingly, the hole current from the p+-type drain layer also decreases. That is, the drain current ID gradually decreases in the period from time t2 to time t3.
The drain current ID flowing in the period after t3 is called tail current.
As such, waste of power (shaded portion in FIG. 11) occurs in the period from time t1 to time t3. The waste of power is a switching loss of IGBT. Further, the waste of power due to the tail current flowing after time t3 becomes large when the tail current flows for a long time even if the tail current is small.
Let the time t3 be the end point of the fall time of the drain current ID. The fall time of the drain current ID is the period beginning from the point of time where the drain current ID is 90% of its full value in the ON state of IGBT to the point of time where the drain current ID is 10% of the same. In FIG. 11, the period from time t2 to time t3 is the fall time.
Furthermore, IGBT maintains its breakdown voltage because of having the n+-type buffer layer 23.
However, for attaining a higher breakdown voltage of IGBT, the nxe2x88x92-type base layer 13 needs a larger thickness. For example, in case the IGBT 20 is an element having the breakdown voltage of 600V, that is, in case its base layer 13 is 60 xcexcm thick, the nxe2x88x92-type base layer 13 must be thicker to increase the breakdown voltage to 600V or more.
Therefore, there is a demand for insulated gate semiconductor devices having low switching loss during turnoff period while being capable of maintaining a lower ON resistance.
There is also a demand for insulated gate semiconductor devices having relatively higher breakdown voltage while maintaining a thin nxe2x88x92-type base layer.
An insulated gate semiconductor device according to an embodiment of the invention comprises: a first base layer of a first conduction type; a second base layer of a second conduction type formed on a first surface of the first base layer; a source layer of the first conduction type selectively formed in a surface region of the second base layer; a drain layer of the second conduction type formed on a second surface of the first base layer opposite from said first surface; and a gate electrode insulated from the source layer, the first base layer and the second base layer and forming in the first base layer a channel electrically connecting the source layer and the second base layer, wherein the injection efficiency of hole current from said drain layer is 0.27 in maximum.
An insulated gate semiconductor device according to a further embodiment of the invention comprises: a first base layer of a first conduction type; a second base layer of a second conduction type formed on a first surface of the first base layer;
a source layer of the first conduction type selectively formed in a surface region of the second base layer; a drain layer of the second conduction type formed on a second surface of the first base layer opposite from said first surface; and a gate electrode insulated from the source layer, the first base layer and the second base layer and forming in the first base layer a channel electrically connecting the source layer and the second base layer, wherein the voltage transiently applied to said device is larger than the static breakdown voltage between the source and the drain when a rated current is turned off under a condition, in which condition an inductance load is from 1 xcexcH to 1 mH and said device is connected said inductance load without using a protective circuit, and wherein thickness of the first base layer is 70 xcexcm in maximum.
An insulated gate semiconductor device according to a still further embodiment of the invention comprises: a first base layer of a first conduction type; a second base layer of a second conduction type formed on a first surface of the first base layer;
a source layer of the first conduction type selectively formed in a surface region of the second base layer; a drain layer of the second conduction type formed on a second surface of the first base layer opposite from said first surface; and a gate electrode insulated from the source layer, the first base layer and the second base layer and forming in the first base layer a channel electrically connecting the source layer and the second base layer, wherein the injection efficiency of hole current from the drain layer is less than 9/19.
An insulated gate semiconductor device according to a yet further embodiment of the invention comprises: a first base layer of a first conduction type; a second base layer of a second conduction type formed on a first surface of the first base layer;
a source layer of the first conduction type selectively formed in a surface region of the second base layer; a drain layer of the first conduction type formed on a first surface of the first base layer and having a thickness not larger than 0.5 xcexcm; and a gate electrode insulated from the source layer, the first base layer and the second base layer and forming in the first base layer a channel electrically connecting the source layer and the second base layer, wherein the voltage transiently applied to said device is larger than the static breakdown voltage between the source and the drain when a rated current is turned off under a condition, in which condition an inductance load is from 1 xcexcH to 1 mH and said device is connected said inductance load without using a protective circuit, and wherein thickness of the first base layer is 70 xcexcm in maximum.
An insulated gate semiconductor device according to a yet further embodiment of the invention comprises: a first base layer of a first conduction type; a second base layer of a second conduction type formed on a first surface of the first base layer; a source layer of the first conduction type selectively formed in a surface region of the second base layer; a drain layer of the second conduction type formed on a second surface of the first base layer opposite from said first surface; and a gate electrode insulated from the source layer, the first base layer and the second base layer and forming in the first base layer a channel electrically connecting the source layer and the second base layer, wherein the total impurity dose of the drain layer is 5xc3x971013 cm2 in maximum.